The present invention relates generally to electrically erasable/programmable read only memories ("EEPROMs") and methods for their fabrication. More specifically, the invention relates to improved tunnel oxide windows on EEPROMs and methods of their fabrication.
As the name implies, electrically erasable/programmable devices can be both erased and programmed electrically without the need for exposure to ultraviolet light or other external factors. This has many advantages, of which the most obvious is the ability to erase or program EEPROM devices in window-less packages (unlike EPROM devices). FIG. 1 depicts a basic two electrode EEPROM structure employed to control programming and erasing. A floating gate 2 forms one electrode and a heavily doped n-type silicon memory diffusion 4 within the silicon substrate 1 forms the other. These two electrodes are separated by a tunnel oxide 6 of 80 .ANG. in thickness, for example. A thick field oxide 8 of approximately 5000 .ANG. in thickness, for example, exists on either edge of the tunnel oxide 6 in order to isolate this device from other devices on the chip.
The EEPROM cell is programmed (turned "off") or erased (turned "on") by charging or discharging, respectively, the floating gate 2. Charge is moved on or off the floating gate 2 by tunneling electrons between the floating gate 2 and a heavily doped memory diffusion 4 in the semiconductor substrate 1. When high voltages are applied to the highly doped diffusion 4 or the floating gate 2, electrons tunnel through tunnel oxide 6 separating the memory diffusion 4 from the floating gate 2. In the EEPROM's "off" state, the floating gate 2 is charged negatively to provide a very high threshold voltage which effectively prevents mobile charge carriers from flowing in a channel region of a read transistor (not shown) having as its gate electrode the floating gate 2. In the "on" state, the positively charged floating gate 2 provides a negative threshold voltage, allowing charge carriers to flow freely in the channel region.
Key to the programming and erasing processes is the tunnel oxide, or more precisely, that portion of the tunnel oxide through which electrons flow--sometimes referred to as a tunnel window. Under normal conditions, the tunnel oxide acts as a dielectric and does not conduct electricity. However, under high electric fields of, for example, 8 to 13 volts across the oxide, electron tunneling occurs through this oxide by a process known as Fowler-Nordheim tunneling. If the tunnel window contains defects (e.g., vacancies, charge trapping centers and dangling bonds), it may allow electrons to leak from a charged floating gate such that the EEPROM rapidly becomes inadvertently erased. The defects provide intermediate energy states allowing the electrons to tunnel more easily across the tunnel window. EEPROM devices having such defects are, of course, unacceptable.
Defects commonly result at the interface of a field oxide region and the tunnel oxide. The thick field oxide introduces severe stress in the materials proximate its "bird beak" protrusion. These stresses in turn can create defects in those portions of the tunnel window abutting the field oxide. The locus of this problem is illustrated in FIG. 1 (depicted as black dots) near the field oxide 8. In a related problem, when two field oxide regions come into close proximity (e.g., less than 0.8 .mu.m separation), their combined stresses may bow the substrate surface together with the overlying tunnel oxide as shown, in an exaggerated fashion, in FIG. 1. This bowing may in its own right introduce defects into the tunnel oxide. While such a bowing may not be evident in relatively large devices, as EEPROMs scale to smaller dimensions (having for example tunnel windows of 0.5.times.0.5 .mu.m) it can become a major concern.
A top view of one commonly used tunnel window design is shown in FIG. 2A. The five features defining the tunnel window 16 are represented here by the outlines of photolithographic masks employed during their formation. Reference numbers designate both the mask regions and their respective on-chip features. The five components are an N.sup.+ memory diffusion 12, a gate oxide 13, a field oxide 14, a tunnel oxide mask 11, and a polysilicon floating gate 15. In this design, a tunnel oxide is grown in the region defined by the tunnel oxide mask 11 over the memory diffusion (MD) 12. The polysilicon floating gate 15 covers all of the tunnel oxide region. The tunnel window 16 is defined by that portion of the tunnel oxide mask 11 lying beyond the field oxide 14 and intersecting the memory diffusion (MD) 12. The tunnel window 16 is therefore bordered by field oxide 14 on two opposing sides. As noted above, the stresses in the tunnel oxide at the field oxide boundary areas can produce defects which may be detrimental to EEPROM function. As further noted above, these defects are increasingly likely with this design as device sizes decrease since smaller tunnel windows require more closely spaced field oxide regions. FIG. 2B shows a cross section 1--1 of FIG. 2A.
A top view of another commonly used tunnel window design is shown in FIG. 2C. Again, the features defining the tunnel window 26 are represented in part by the outlines of photolithographic masks employed during their formation, with the reference numbers designating both the mask regions and their respective on-chip features. In this design, a tunnel oxide 21 is grown within a region of gate oxide 22, over a memory diffusion (MD) 23, but removed from the edges of a field oxide 24. A polysilicon floating gate 25 covers the entire tunnel oxide region and a large part of the surrounding area. In this design, the tunnel window 26 is determined by the size of the hole in the tunnel oxide mask (the mask applied prior to etching the gate oxide in preparation for the growth of the tunnel oxide). Therefore the tunnel oxide is entirely coincident with the tunnel window, which separates the MD 23, below, and floating gate 25, above. FIG. 2D shows a cross section 2--2 of FIG. 2C.
While this design avoids the problems associated with tunnel oxide defects caused at the field oxide edges, it presents similar scaling problems since it becomes increasingly difficult to define and etch smaller square openings for the tunnel oxide mask. This design approach suffers from the additional problem that it produces a large overlap of polysilicon floating gate and MD separated by gate (or MD) oxide. The result is that there is a relatively high gate capacitance at the tunnel oxide node of the EEPROM. This gate capacitance will degrade the performance of the cell.
Thus, there is a need for an improved tunnel window design which does not have an unacceptably high capacitance and which can scale to smaller device sizes without introducing unacceptable defects in active portions of the tunnel oxide.